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) ,17(55837 9(&725 $''5(66(6 Table F-1 lists all processor interrupts according to their bit position in the IRPTL and IMASK registers. Four memory locations separate each interrupt vector. For each vector, Table F-1 also lists the address, mne- monic (not required by the assembler), and priority. The addresses in the vector table represent offsets from a base address. For an interrupt vector table in internal memory, the base address is 0x0000 8000, the beginning of Block 0. For an interrupt vector table in external memory, the base address is 0x0002 0000. Table F-1. IRPTL/IMASK interrupt vectors and priorities Bit Address Name Description Priority 0 0x00 1 0x04 RSTI Reset (read-only, non- Highest maskable) 2 0x08 3 0x0C SOVFI Status stack or loop stack overflow or PC full 4 0x10 TMZHI Timer high priority option 5 0x14 VIRPTI Vector interrupt 6 0x18 IRQ2I IRQ2 asserted 7 0x1C IRQ1I IRQ1 asserted Table F-1. IRPTL/IMASK interrupt vectors and priorities (Cont’d) Bit Address Name Description Priority 8 0x20 IRQ0I IRQ0 asserted 9 0x24 10 0x28 SPR0I DMA channel 0/1; SPORT0 receive A&B 11 0x2C SPR1I DMA channel 2/3; SPORT1 receive A&B 12 0x30 SPT0I DMA channel 4/5; SPORT0 transmit A&B 13 0x34 SPT1I DMA channel 6/7; SPORT1 transmit A&B 14 0x38 15 0x3C 16 0x40 EP0I DMA channel 8; Ext