VHDL入门教程课件.ppt

3.3.3 例化语句 3.4 计数器设计 思考题 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY shift1 IS PORT ( d: IN STD_LOGIC_VECTOR ( 7 DOWNTO 0); clr, clk, load, dir, sr, sl: IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END shift1; ARCHITECTURE arc OF shift1 IS SINGAL a: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN q<= a; PROCESS (clr,clk) BEGIN IF (clr=‘0’) THEN a<=; ELSEIF (clk’EVENT) AND (clk=‘1’) THEN IF (load=‘0’) THEN a<=d; ELSEIF (load=‘1’) AND (dir=‘0’) THEN FOR I IN 7 DOWNTO 1 LOOP a(i) <=a (i-1); END LOOP; a(0)<= sr; ELSEIF (load=‘1’) AND(dir=‘1’) THEN FOR i IN 0 TO 6 LOOP a (i )<=a(i+1); END LOOP; a(7)<=sl; END IF; END IF; END PROCESS; END arc; 题5： 【例6-9】 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY DFF3 IS PORT ( CLK,D1 : IN STD_LOGIC ; Q1 : OUT STD_LOGIC); END ; ARCHITECTURE bhv OF DFF3 IS BEGIN PROCESS (CLK) VARIABLE A,B : STD_LOGIC ; BEGIN IF CLK'EVENT AND CLK ='1' THEN A:= D1; B := A; Q1 <= B; END IF; END PROCESS ; END ; 由于A，B是变量，它们的赋值更新是立即发生的。 当3条语句顺序执行时，A和B 有了传递数据的功能。 实际执行时，在一个δ时刻内D1传给A，A 传给B，B 传给Q1。A和B只担当了D1数据的暂存单元，Q1被更新的值是上一时钟周期的D1。 D Q D1 CLK Q1 二 、信号与变量在延时特性上的区别 【例6-10】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4 IS PORT (i0, i1, i2, i3, a, b : IN STD_LOGIC; q : OUT STD_LOGIC); END mux4; ARCHITECTURE body_mux4 OF mux4 IS signal muxval : integer range 7 downto 0; BEGIN process(i0,i1,i2,i3,a,b) begin muxval <= 0; if (a = '1') then muxval <= muxval + 1; end if; if (b = '1') then muxval <= muxval + 2; end if; case muxval is when 0 => q <= i0; when 1 => q <= i1; when 2 => q <= i2; when 3 => q <= i3; when others => null; end case; end process; END body_mux4; 【例6-11】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4 IS PORT (i0, i1, i2, i3, a, b : IN STD_LOGIC; q : OUT STD_LOGIC);