主板时钟发生器ics1531pb.pdfVIP

Integrated Circuit Systems, . ICS1531 Type: Product Brief Chip Stage: Preliminary Product Preview Triple 8-bit 100/140/165 MSPS ADC with Line-Locked Clock Generator General Description Features The ICS1531- 100, -140 and -165 chips are each •3-channel 8-bit og-to-digital conversion up to 165 MHz high-performance, cost-effective, 3-channel, 8-bit og-to -digital converters with an integrated •Uses 3.3 VDC. Digital inputs are 5-V tolerant, which line-locked clock generator. They are part of a family saves design and manufacturing costs. of chips for high-resolution applications that use •Direct connection to og input data (no external og inputs, such as LCD monitors, LCD projectors, pre-amplification needed) sm a d is ys, and p roj ec t ion TV s. U sin g • amplifier: 500-MHz og bandwidth, low-voltage CMOS mixed-signal technology, they are software-adjustable gain an effective d apture solution for VGA to UXGA. •Dynamic Phase Adjust (DPA) for software-adjustable og sample points The ICS1531 chips offer og-to-digital data conversion and synchronized pixel-clock generation up •Software selectable: One pixel per clock (for 24-bit to 165 Mega samples per second, (MSPS) or 165 MHz. pixels) or two pixels per clock (for a total of 48 bits) The Dynamic Phase Adjust (DPA) circuitry allows •Internal clamp