文件第18静态时序分析本章目标描述一般sta以及对.pdfVIP

Chapter 18 Static Timing ysis The goal of this chapter is to describe general static timing ysis (STA) as well as methods for performing static timing ysis on complex circuit configurations not commonly discussed in the context of STA such as asynchronous circuits, latches, and combinatorial feedback paths. Note that these latter structures are typically not recommended for FPGA designers mainly because of the difficulty in implementing them correctly. However, an advanced designer can use these structures if necessary as long as the associated issues (particularly the timing ysis) are understood. During the course of this chapter, we will discuss the following topics: . Summary of basic static timing ysis . Understanding latches in STA . Handling asynchronous circuits in STA with combinatorial logic or event- driven clocks This chap ssumes the reader is already familiar with general static timing ysis but will provide a brief summary of the basic concepts. 18.1 STANDARD YSIS Static timing ysis, as it is referred to in this chapter, is the comprehensive ysis of all timing paths in a design relative to a set of constraints so as to determine whether a design is “timing compliant.” The basic paths encountered by an FPGA designer will be input to flip-flop, flip-flop to flip-flop, and flip-flop to output as illustrated in Figure 18.1. These have associated input delay, output delay, setup, and hold timing requirements. The setup timing ysis refers to the long-path ysis, and the hold timing refers to the short-path ysis. The um frequency is set by the longest path in the design, which is also referred to as the critical path. The Advanced FPGA Design . By Steve Kilts Copyrigh