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Laboratory Exercise 4 Polling and Interrupts The purpose of this exercise is to learn how to send and receive data to/from I/O devices. There are two methods used to indicate whether or not data can be sent or is ready to be received to/from I/O devices. The first method, polling, is where the processor queries devices to see if they can receive data or have data available. The second method, interrupts, is when devices indicate to the processor that they can receive data or that they have data available, without the processor explicitly requesting. A simple and commonly used scheme for transferring data between a processor and an I/O device is known as the Universal Asynchronous Receiver Transmitter (UART). A UART interface (circuit) is placed between the processor and the I/O device. It handles data one 8-bit character at a time. The transfer of data between the UART and the processor is done in parallel fashion, where all bits of a character are transferred at the same time using separate wires. However, the transfer of data between the UART and the I/O device is done in bit-serial fashion, transferring the bits one at a time. Altera’s SOPC Builder can implement an interface of the UART type for use in Nios II systems, which is called the JTAG UART. This circuit can be used to provide a connection between a Nios II processor and the host computer connected to Altera’s DE2_115 board. Figure 1 shows a block diagram of the JTAG UART circuit. On one side the JTAG UART connects to the Avalon switch fabric, while on the other side it connects the host computer via the USB-Blaster interface. The JTAG UART core contains two registers: Data and Control, which are accessed by the processor as memory locations. The address of the Control register is 4 bytes higher than the address assigned to the Data register. The core a