【word版可编辑】12位高速流水线ADC设计.docx

摘要 模数转换器（ADC）作为数字信号处理系统的前端核心器件，是连接模拟世界与数字世界的桥 梁。随着无线通信技术以及CMOS工艺技术的推进，ADC也朝着高速、高精度的方向发展。在众 多的ADC结构中，流水线结构因在速度、精度、面枳以及功耗之间有着较好的折衷，因而成为目前 髙速高精度ADC研究的主流架构。本文采用40nm CMOS工艺，设计了一款12位高速流水线ADC。 论文在介绍流水线ADC的基本工作原理及相应工作时序的基础上，对影响高速高精度ADC的 各种非理想因素进行深入的讨论。基于上述理论的分析，本文的12位高速流水线ADC系统采用 SHA-lcss架构，流水级转换采用2+3+3+3+3的组合方式，釆样电容采用了逐级缩减技术。 为了减小比较器失调等非理想因素的影响，每个流水级转换电路都采用了数字冗余技术。由于 小尺寸工艺节点以及低电源电压对高增益宽带宽运放的限制，本文仅采用两级密勒补卷运放来保证 高速流水线ADC对运放带宽的需求。对于运放增益不足以及电容失配等因素造成的级间増益误差， 通过在数字域测量误差大小，并设计了一个可编程的反馈电容电路来校准该増益误差。 仿真结果表明，本文所设计的12位高速流水线ADC在1.1V电源电压下，可以输入的最大差分 电压为1.4V。在300MHz采样频率下，可以获得10.74 bit的ENOB. 70.83 dB的SFDR。电路的整 体功耗约为104mW.核心面积约为0.18mn?。 关健词：流水线ADC运算放大器增益校准数字校正 PAGE PAGE # PAGE PAGE # Abstract Abstract As the front-end core device of the digital signal processing system, lhe analog-lo-digital converter (ADC) is a bridge connecting lhe analog world and the digital world. With the development of wireless communication technology and CMOS process technology, ADCs arc also moving toward high speed and high resolution. In many ADC struclures, the pipeline structure has a good compromise among speed, resolution, area and power consumption, and thus is the mainstream architecture of high-speed and high-resolution ADC research. In this dissertation , a 12-bit high-speed pipeline ADC is designed using 40 nm CMOS technology. Firstly, the basic working principle of the pipeline ADC and the corresponding time sequence arc introduced. And then in-depth research and analysis on various non-idcal factors a fleeting high-speed and high-resolution ADC arc conducted. Based on these theoretical studies, the SHA-lcss architecture and the combination of 2+3+3+3+3+3 pipeline level conversion are adopted in lhe design of 12-bit high-speed pipeline ADC. Besides, stage scaling-down technique is also adopted in the design. In order to reduce the influence of non-ideal factors such as comparator offset voltage, digital redundancy technology is used in pipeline stage. Due to the low-scale process node and l